Resume

Accomplishments

• Developed electroless nickel bath inhibitor to control a surface-loading phenomenon on semiconductor deposition processes. With standard inhibitors electroless nickel plating on wafers would not have been manufacturable.

• Lead development and implementation of tin-silver and tin-copper plating baths and compatible bus (seed) metal etchants for manufacture of lead-free semiconductor devices for Flip-Chip assembly. Freescale continues to use  this lead-free plating process on its Flip -Chip wafers.

• Initiated development of revolutionary polymer wafer fabrication processes for Freescale’s innovative “Redistributed Chip Package” (RCP).

• Designed and built unique tools for the manual fabrication of polymer wafers (panels) during the development of a new packaging process. The tool designs were later implemented into automated robotic tooling. There are three patents pending.

• Created non-degrading carrier attach and release process to temporarily allow panels to be held rigid during high-temperature front side circuit and dielectric build-up processes. Worked with the tool and chemical manufacturers to fully automate process step. Patent pending.

• Determined material sources and managed initial materials list for RCP processing. This list was used to create a bill of materials (BOM), materials inventory planning, and just-in-time delivery. Directed facility planners and contractors in design and layout of chemical storage and waste treatment facilities for the RCP manufacturing line.

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Education

Master of Science, Chemistry....................................... Arizona State University, Tempe, Arizona
Bachelor of Science, Chemistry..................................... University of Cincinnati, Cincinnati, Ohio

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Professional Experience

Faraday Solutions LLC, Chandler, AZ ................................................... March 2009 - Present
Founder, Materials and Plating Specialist.  Created consulting business to assist companies in determining materials sets and processes for development of solar, medical and semiconductor products.

•Currently developing process and material sets for potential medical device application. – Quest Product Development Corp., Denver, CO.

 

Freescale Semiconductor Inc., Tempe, AZ ........................................................... 2004 - 2009
Distinguished Member of the Technical Staff. Initiated development of revolutionary polymer wafer fabrication processes for Freescale’s innovative “Redistributed Chip Package” (RCP). Freescale additionally intends to license RCP to subcontractors.

• Designed and built unique tools for manual fabrication of polymer wafers (panels) during development of new packaging process. Concepts and ideas were implemented into automated robotic tooling. Three patents pending.

• Created non-degrading carrier attach and release process to temporarily allow panels to be held rigid during high-temperature front side circuit and dielectric build-up processes. Worked with the tool and chemical manufacturers to fully automate process step. Patent pending.

• Developed process to prevent epoxy resin from bleeding onto semiconductor die bond pads during cure. This process was crucial to improving yield of RCP packages. Patent pending.

• Determined source and managed initial materials list for RCP processing. This list was used to create a bill of materials (BOM), materials inventory planning, and just-in-time delivery. Determined chemical usage rates and wastewater treatment plans based on the material data in this list.

• Directed facility planners and contractors in design and layout of chemical storage and waste Treatment facilities for the RCP manufacturing line.

 

Motorola Inc. Semiconductor Products Sector (SPS), Tempe, AZ & Austin, TX...... 1982 - 2004
Senior Member of the Technical Staff................................................................... 2002 - 2004
• Managed implementation of lead-free plating process into Flip-Chip manufacturing operations for Motorola Semiconductor Products and managed the project for the initial development of RCP.
• Directed research and development of polymer encapsulation, sputtered metal deposition, copper plating processes and selection of dielectric for demonstration of the feasibility of the “RCP” process.
• Lead development and implementation of tin-silver and tin-copper plating baths and compatible bus (seed) metal etchants for manufacture of lead-free semiconductor devices for Flip-Chip assembly. Freescale continues to use the lead-free plating process on all of its Flip-Chip devices.

Principal Staff Scientist, Tempe, AZ....................................................................... 1997 - 2002
• Provided failure analysis support for semiconductor package development team. •Developed extremely low temperature grinding and polishing methods to allow cross-sectioning of the interfaces between hard and soft materials such as indium solder or polymeric layers in contact with silicon. Patented.
• Performed SEM/EDX characterization on brittle solder joints and determined the cause to be chemical attack and depletion of elemental nickel. Proposed successful solutions to improve joint reliability and saved Motorola over $5M from loss of business due to product returns.
• Solved GaAs through-via clearing and shorting issue by recognizing an interaction between gold and resist during plasma strip. Implemented the use of a gold before plasma eliminating the issue and saving Motorola loss of a $10M customer.

Senior Staff Scientist,Tempe, AZ/Austin, TX ......................................................... 1995 - 1997
• Created and transferred “Low-Cost Bump” process to Motorola’s manufacturing facility in Austin, Texas.
• Developed electroless nickel bath inhibitor to control a poorly understood phenomenon in electroless metal deposition processes. Without this inhibitor electroless nickel plating on wafers would not have been manufacturable.

Engineer/ Sr. Scientist, Phoenix, AZ ..................................................................... 1982 - 1995
• Assumed different engineering roles in semiconductor product development eventually focusing on Flip-Chip package development.
Co-invented solder bumping process for Flip-Chip attach of a GaAs optical display for use in the worlds first sub-miniature monochromatic digital display. Patented.
• Developed two etchant formulations and processes to allow manufacture of plated inductors on silicon. Etchants and processes are also used in the fabrication on-wafer chip-array burn-in circuitry. Patented.
• Developed a fountain wafer plating cell to control flow and current effects during electrolytic deposition of soft metals such as indium tin and lead. Patented.

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Patents

• 2010/0081234 Method of forming a package with exposed component surfaces
• 2008/0182363 Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer
• 2007/0210427 Warp compensated package and method
• 2010/0078808 Packaging having two devices and method of forming thereof
• 2009/0061564 Method of packaging an integrated circuit device
• 2009/0057849 Interconnect in a multi-element package
• 7802359 Electronic assembly manufacturing method
• 7741151 Integrated circuit package formation
• 7595226 Method of packaging an integrated circuit die
• 7442581 Flexible carrier and release method for high volume electronic package
• 7078796 Corrosion-resistant copper bond pad and integrated device
• 6974776 Activation plate for electroless and immersion plating of integrated circuits
• 6953985 Wafer level MEMS packaging
• 6949398   Low cost fabrication and assembly of lid for semiconductor devices
• 6302775             Apparatus and method for cold cross-sectioning of soft materials
• 5912510             Bonding structure for an electronic device
• 5674780             Method of forming an electrically conductive polymer bump over an aluminum
• 5593903             Method of forming contact pads for wafer level testing and burn-in of ...
• 5587342 Method of forming an electrical interconnect
• 5411400 Interconnect system for a semiconductor chip and a substrate
• 5409567 Method of etching copper layers
• 5391285 Adjustable plating cell for uniform bump plating of semiconductor wafers
• 5072873 Device for solder removal
• 5028454 Electroless plating of portions of semiconductor devices and the like
• 4946376 Backside metallization scheme for semiconductor devices
• 4787958 Method of chemically etching TiW and/or TiWN

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Publications

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Professional Societies

IEEE-CPMT, MEPTEC, IMAPS, American Chemical Society, ChemPharma

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Training

Six Sigma Methodology, Green Belt in Statistics, Chemical Waste Handling

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